The invention is in the field of nonvolatile memory devices, and relates more specifically to a nonvolatile memory cell of the type having a single lateral transistor.
Memory cells having a single lateral transistor, such as EEPROM devices, are generally well known in the art. Several different single-transistor nonvolatile memory cells, as well as memory arrays using such cells, are shown in U.S. Pat. No. 4,698,787, incorporated herein by reference. This patent shows and describes various nonvolatile memory devices of the general type disclosed herein, their construction and method of operation, thus providing a foundation of information for understanding the present invention.
As noted in the above-mentioned reference, an object in designing such memory cells is to create a memory cell design which will require substantially lower programming and erasing voltages. More particularly, programming voltage should be low so that programming speed is fast, and erasing voltage should be low so that the silicon area needed for the circuitry required to generate such voltage is reduced.
As detailed in the cited reference, programming and erasing operations in typical older prior-art devices, such as those shown in FIGS. 1 and 2 of the reference, require either two voltages, one between 8 and 12 volts and a second between 13 and 21 volts, or else a single voltage of approximately 20 volts, depending upon the mechanism used for programming and erasing. Devices made in accordance with the invention disclosed in the reference, by contrast, require that programming voltages be in the range of 10 to 13 volts, with practical present-day devices typically using 12 to 13 volts. In addition, devices of this type typically employ erase voltage levels of about 15 to 25 volts, and it would be desirable for the reasons detailed above to further reduce both the programming and erasing voltage levels.
It is therefore an object of the present invention to provide a nonvolatile memory cell such as an EEPROM device having a single lateral transistor in which lower programming and erasing voltages than those used in the prior art can be employed.
It is a further object of the invention to provide a nonvolatile memory cell having a relatively fast programming speed and in which the silicon area required for the circuitry necessary to generate the erasing voltage is small.
In accordance with the invention, these objects are achieved by a new nonvolatile memory cell which has a unique configuration in the region of the gate structure that permits the use of lower programming and erasing voltages to achieve a fast and compact device.
The advantageous features of the present invention are achieved in a nonvolatile memory cell of the type having a single lateral transistor in a semiconductor body having a major surface and having source and drain regions separated by a channel region, with an insulated floating gate over the channel region and an insulated control gate over the floating gate. The floating gate extends over substantially its entire length at a substantially constant distance from the major surface of the silicon body, and the floating gate and the major surface are provided with similarly-contoured corners adjacent ends of the source and drain regions which are alongside the channel region.
In a preferred embodiment of the invention, a shallow groove is provided in the major surface of the semiconductor body at the channel region and overlapping the ends of the source and drain regions along the side of the channel region, and the corners of the floating gate and the major surface are concave.
In a further preferred embodiment of the invention, the major surface of the semiconductor body is contoured in a stepwise fashion such that the source region is higher than the drain region, with the corner of the floating gate and the major surface adjacent the source region being concave and the corner of the floating gate and the major surface adjacent the drain region being convex.
In each of the foregoing embodiments, the thickness of the gate oxide between the floating gate and the channel region may advantageously be in the range of about 50 to 200 Angstroms.